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| ICX434DQN Diagonal 5.68mm (Type 1/3.2) Frame Readout CCD Image Sensor with Square Pixel for Color Cameras Description The ICX434DQN is a diagonal 5.68mm (Type 1/3.2) interline CCD solid-state image sensor with a square pixel array and 2.02M effective pixels. Frame readout allows all pixels' signals to be output independently within approximately 1/7.5 second. Also, the adoption of high frame rate readout mode supports 30 frames per second which is four times the speed in frame readout mode. This chip features an electronic shutter with variable charge-storage time. Adoption of a design specially suited for frame readout ensures a saturation signal level equivalent to when using field readout. High resolution and high color reproductivity are achieved through the use of R, G, B primary color mosaic filters. Further, high sensitivity and low dark current are achieved through the adoption of Super HAD CCD technology. This chip is suitable for applications such as electronic still cameras, PC input cameras, etc. 16 pin SOP (Plastic) Pin 1 2 Features V * Supports frame readout * High horizontal and vertical resolution * Supports high frame rate readout mode: 30 frames/s * Square pixel 4 * Horizontal drive frequency: 18MHz 48 H Pin 9 * No voltage adjustments (reset gate and substrate bias are not adjusted.) * R, G, B primary color mosaic filters on chip Optical black position * High color reproductivity, high sensitivity, low smear * Continuous variable-speed shutter (Top View) * Low dark current, excellent anti-blooming characteristics * 16-pin high-precision plastic package (top/bottom dual surface reference possible) Device Structure * Interline CCD image sensor * Image size: Diagonal 5.68mm (Type 1/3.2) * Total number of pixels: 1688 (H) x 1248 (V) approx. 2.11M pixels * Number of effective pixels: 1636 (H) x 1236 (V) approx. 2.02M pixels * Number of active pixels: 1620 (H) x 1220 (V) approx. 1.98M pixels * Chip size: 5.27mm (H) x 4.40mm (V) * Unit cell size: 2.8m (H) x 2.8m (V) * Optical black: Horizontal (H) direction: Front 4 pixels, rear 48 pixels Vertical (V) direction: Front 10 pixels, rear 2 pixels * Number of dummy bits: Horizontal 28 Vertical 1 (even fields only) * Substrate material: Silicon 10 Super HAD CCD is a trademark of Sony Corporation. The Super HAD CCD is a version of Sony's high performance CCD HAD (HoleAccumulation Diode) sensor with sharply improved sensitivity by the incorporation of a new semiconductor technology developed by Sony Corpration. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E02202 ICX434DQN VOUT GND V1B V1A V3B V3A 2 B G B G B G 8 7 6 5 V2 4 3 1 G B G B G B G G R G R G R Vertical register R G R G R Horizontal register Note) 9 10 11 12 13 14 15 16 : Photo sensor RG Pin Description Pin No. 1 2 3 4 5 6 7 8 Symbol V4 V3A V3B V2 V1A V1B GND VOUT Description Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock GND Signal output Pin No. 9 10 11 12 13 14 15 16 Symbol VDD GND SUB CSUB VL RG H1 H2 Description Supply voltage GND Substrate clock Substrate bias1 Protective transistor bias Reset gate clock Horizontal register transfer clock Horizontal register transfer clock 1 DC bias is generated within the CCD, so that this pin should be grounded externally through a capacitance of 0.1F. Absolute Maximum Ratings Item VDD, VOUT, RG - SUB V1A, V1B, V3A, V3B - SUB V2, V4, VL - SUB H1, H2, GND - SUB CSUB - SUB VDD, VOUT, RG, CSUB - GND V1A, V1B, V2, V3A, V3B, V4 - GND H1, H2 - GND V1A, V1B, V3A, V3B - VL V2, V4, H1, H2, GND - VL Voltage difference between vertical clock input pins H1 - H2 H1, H2 - V4 Ratings -40 to +12 -50 to +15 -50 to +0.3 -40 to +0.3 -25 to -0.3 to +22 -10 to +18 -10 to +6.5 -0.3 to +28 -0.3 to +15 to +15 -6.5 to +6.5 -10to +16 -30 to +80 -10 to +60 -10 to +75 Unit V V V V V V V V V V V V V C C C Remarks Against SUB Against GND Against VL Between input clock pins Storage temperature SUB CSUB GND VDD H1 H2 VL V4 Note) Block Diagram and Pin Configuration (Top View) 2 Guaranteed temperature of performance Operating temperature 2 +24V (Max.) when clock width < 10s, clock duty factor < 0.1%. +16V (Max.) is guaranteed for turning on or off power supply. -2- ICX434DQN Bias Conditions Item Supply voltage Protective transistor bias Substrate clock Reset gate clock Symbol VDD VL SUB RG Min. 14.55 Typ. 15.0 1 2 2 Max. 15.45 Unit V Remarks 1 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same voltage as the VL power supply for the V driver should be used. 2 Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated within the CCD. DC Characteristics Item Supply current Clock Voltage Conditions Item Readout clock voltage Symbol VVT VVH1, VVH2 VVH3, VVH4 VVL1, VVL2, VVL3, VVL4 VV Vertical transfer clock voltage VVH3 - VVH VVH4 - VVH VVHH VVHL VVLH VVLL VH Horizontal transfer clock voltage VHL VCR VRG Reset gate clock voltage VRGLH - VRGLL VRGL - VRGLm Substrate clock voltage VSUB 21.5 22.5 3.0 -0.05 0.5 3.0 3.3 0 1.65 3.3 3.6 0.4 0.5 23.5 Min. 14.55 -0.05 -0.2 -8.0 6.8 -0.25 -0.25 Typ. 15.0 0 0 -7.5 7.5 Max. 15.45 0.05 0.05 -7.0 8.05 0.1 0.1 0.5 0.5 0.5 0.5 3.6 0.05 Unit V V V V V V V V V V V V V V V V V V Waveform diagram 1 2 2 2 2 2 2 2 2 2 2 3 3 3 4 4 4 5 Low-level coupling Low-level coupling Cross-point voltage High-level coupling High-level coupling Low-level coupling Low-level coupling VVL = (VVL3 + VVL4)/2 VV = VVHn - VVLn (n = 1 to 4) VVH = (VVH1 + VVH2)/2 Remarks Symbol IDD Min. Typ. 6.5 Max. Unit mA Remarks -3- ICX434DQN Clock Equivalent Circuit Constant Item Capacitance between vertical transfer clock and GND Symbol CV1A, CV3A CV1B, CV3B CV2, CV4 CV1A2, CV3A4 CV1B2, CV3B4 CV23A, CV41A CV23B, CV41B Capacitance between vertical transfer clocks CV1A3A CV1B3B CV1A3B, CV1B3A CV24 CV1A1B, CV3A3B Capacitance between horizontal transfer CH1 clock and GND CH2 Capacitance between horizontal transfer CHH clocks Capacitance between reset gate clock and GND Capacitance between substrate clock and GND CRG CSUB R1A, R3A Vertical transfer clock series resistor R1B, R3B R2, R4 Vertical transfer clock ground resistor Horizontal transfer clock series resistor V2 R2 CV1A3A CV23B CV23A V3A R3A RH CV1B2 CV1A CV1A1B CV1B3A CV1B CV41A V1B R1B CV4 CV41B RGND CV1B3B R4 CV2 CV3A CV3A3B CV1A3B CV3B CV3A4 R3B V3B CV3B4 H1 CHH RH H2 Min. Typ. 680 1500 1500 100 220 30 56 12 82 39 100 30 30 30 56 5 470 270 110 56 10 15 Max. Unit pF pF pF pF pF pF pF pF pF pF pF pF pF pF pF pF pF Remarks RGND RH CV24 V1A R1A CV1A2 CH1 CH2 V4 Vertical transfer clock equivalent circuit -4- Horizontal transfer clock equivalent circuit ICX434DQN Drive Clock Waveform Conditions (1) Readout clock waveform 100% 90% II II M VVT 10% 0% tr twh tf 0V M 2 (2) Vertical transfer clock waveform V1A, V1B V3A, V3B VVH1 VVHH VVH VVHL VVHH VVHH VVHL VVHL VVH3 VVHH VVHL VVH VVL1 VVLH VVL3 VVLH VVLL VVL VVL VVLL V2 VVHH VVHH V4 VVHH VVHH VVH VVHL VVH VVH2 VVHL VVHL VVH4 VVHL VVL2 VVLH VVLH VVLL VVL VVL4 VVLL VVL VVH = (VVH1 + VVH2)/2 VVL = (VVL3 + VVL4)/2 VV = VVHn - VVLn (n = 1 to 4) -5- ICX434DQN (3) Horizontal transfer clock waveform tr H2 90% VCR VH 10% H1 two VH 2 twh tf twl VHL Cross-point voltage for the H1 rising side of the horizontal transfer clocks H1 and H2 waveforms is VCR. The overlap period for twh and twl of horizontal transfer clocks H1 and H2 is two. (4) Reset gate clock waveform tr twh tf RG waveform VRGH twl VRG Point A VRGLH VRGLL VRGLm VRGL VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and VRGLL. VRGL = (VRGLH + VRGLL)/2 Assuming VRGH is the minimum value during the interval twh, then: VRG = VRGH - VRGL Negative overshoot level during the falling edge of RG is VRGLm. (5) Substrate clock waveform 100% 90% M VSUB 10% 0% M 2 tf VSUB tr twh (A bias generated within the CCD) -6- ICX434DQN Clock Switching Characteristics (Horizontal drive frequency:18MHz) Item Readout clock Vertical transfer clock Horizontal transfer clock During imaging Symbol VT V1A, V1B, V2, V3A, V3B, V4 H1 H2 14 19.5 14 19.5 5.56 5.56 7 10 37 14 19.5 14 19.5 8.5 14 8.5 14 0.01 0.01 4 0.5 twh twl tr tf Unit Remarks s During readout When using CXD1267AN Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. 1.36 1.56 0.5 0.5 15 250 ns 8.5 14 8.5 14 0.01 0.01 5 0.5 s ns s ns tf tr - 2ns During H1 parallel-serial H2 conversion RG SUB Reset gate clock Substrate clock 1.7 3.6 During drain charge Item Symbol two Min. Typ. Max. 12 19.5 Unit ns Remarks Horizontal transfer clock H1, H2 Spectral Sensitivity Characteristics (excludes lens characteristics and light source characteristics) 1.0 G 0.9 0.8 0.7 Relative Response 0.6 0.5 0.4 0.3 0.2 0.1 0 400 B R 450 500 550 Wave Length [nm] 600 650 700 -7- ICX434DQN Image Sensor Characteristics Item G sensitivity Sensitivity comparison Saturation signal Smear R B Symbol Sg Rr Rb Vsat Sm Min. 200 0.46 0.33 420 -86 -74 -76 -64 20 25 8 4 3.8 3.8 3.8 0.5 Typ. 250 0.72 0.59 mV dB % % mV mV % % % % Max. Unit mV Measurement method 1 1 1 2 3 4 4 5 6 7 7 7 8 Ta = 60C (Ta = 25C) Remarks 1/30s accumulation Frame readout mode1 High frame rate readout mode Zone 0 and I Zone 0 to II' Ta = 60C, 15 frame/s Ta = 60C, 15 frame/s,2 Video signal shading Dark signal Dark signal shading Line crawl G Line crawl R Line crawl B Lag SHg Vdt Vdt Lcg Lcr Lcb Lag 1 After closing the mechanical shutter, the smear can be reduced to below the detection limit by performing vertical register sweep operation. 2 Excludes vertical dark signal shading caused by vertical register high-speed transfer. Zone Definition of Video Signal Shading 1636 (H) 8 8 8 V 10 H 8 H 8 1236 (V) Zone 0, I Zone II, II' V 10 8 Ignored region Effective pixel region Measurement System CCD signal output [A] Gr/Gb CCD C.D.S AMP S/H R/B S/H R/B channel signal output [C] Gr/Gb channel signal output [B] Note) Adjust the amplifier gain so that the gain between [A] and [B], and between [A] and [C] equals 1. -8- ICX434DQN Image Sensor Characteristics Measurement Method Color coding of this image sensor & Readout B2 Gb R B1 Gb R B Gr B Gr Gb R Gb R B Gr B Gr A1 A2 The primary color filters of this image sensor are arranged in the layout shown in the figure on the left (Bayer arrangement). Gr and Gb denote the G signals on the same line as the R signal and the B signal, respectively. For frame readout, the A1 and A2 lines are output as signals in the A field, and the B1 and B2 lines in the B field. Horizontal register Color Coding Diagram Readout modes The diagram below shows the output methods for the following two readout modes. Frame readout mode 1st field 9 8 7 6 5 4 3 2 1 VOUT R G R G R G R G R G B G B G B G B G VOUT High frame rate readout mode 2nd field 9 8 7 6 5 4 3 2 1 R G R G R G R G R G B G B G B G B G VOUT 9 8 7 6 5 4 3 2 1 R G R G R G R G R G B G B G B G B G Note) Blacked out portions in the diagram indicate pixels which are not read out. Output starts from the line 2 in high frame rate readout mode 1. Frame readout mode In this mode, all pixel signals are divided into two fields and output. All pixel signals are read out independently, making this mode suitable for high resolution image capturing. 2. High frame rate readout mode All effective area signals are output in 1/4 the period for frame readout mode by reading out two lines for every eight lines. The number of output lines is 309 lines. This readout mode emphasizes processing speed over vertical resolution. -9- ICX434DQN Measurement conditions 1) In the following measurements, the device drive conditions are at the typical values of the bias and clock voltage conditions, and the frame readout mode is used. 2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical black level (OB) is used as the reference for the signal output, which is taken as the value of the Gr/Gb channel signal output or the R/B channel signal output of the measurement system. Definition of standard imaging conditions 1) Standard imaging condition I: Use a pattern box (luminance: 706cd/m2, color temperature of 3200K halogen source) as a subject. (Pattern for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter and image at F5.6. The luminous intensity to the sensor receiving surface at this point is defined as the standard sensitivity testing luminous intensity. 2) Standard imaging condition II: Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles. Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is adjusted to the value indicated in each testing item by the lens diaphragm. 3) Standard imaging condition III: Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles. Use a testing standard lens (exit pupil distance -33mm) with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is adjusted to the value indicated in each testing item by the lens diaphragm. 1. G sensitivity, sensitivity comparison Set to standard imaging condition I. After selecting the electronic shutter mode with a shutter speed of 1/100s, measure the signal outputs (VGr, VGb, VR and VB) at the center of each Gr, Gb, R and B channel screen, and substitute the values into the following formulas. VG = (VGr + VGb)/2 Sg = VG x 100/30 [mV] Rr = VR/VG Rb = VB/VG 2. Saturation signal Set to standard imaging condition II. After adjusting the luminous intensity to 20 times the intensity with the average value of the Gr signal output, 150mV, measure the minimum values of the Gr, Gb, R and B signal outputs. 3. Smear Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, first adjust the average value of the Gr signal output to 150mV. Measure the average values of the Gr signal output, Gb signal output, R signal output and B signal output (Gra, Gba, Ra, Ba), and then adjust the luminous intensity to 500 times the intensity with the average value of the Gr signal output, 150mV. After the readout clock is stopped and the charge drain is executed by the electronic shutter at the respective H blankings, measure the maximum value (VSm [mV]) independent of the Gr, Gb, R and B signal outputs, and substitute the values into the following formula. Sm = 20 x log Vsm / ( 1 1 Gra + Gba + Ra + Ba x x 500 10 4 - 10 - ) [dB] (1/10V method conversion value) ICX434DQN 4. Video signal shading Set to standard imaging condition III. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity so that the average value of the Gr signal output is 150mV. Then measure the maximum (Grmax [mV]) and minimum (Grmin [mV]) values of the Gr signal output and substitute the values into the following formula. SHg = (Grmax - Grmin)/150 x 100 [%] 5. Dark signal Measure the average value of the signal output (Vdt [mV]) with the device ambient temperature 60C and the device in the light-obstructed state, using the horizontal idle transfer level as a reference. 6. Dark signal shading After measuring 5, measure the maximum (Vdmax [mV]) and minimum (Vdmin [mV]) values of the dark signal output and substitute the values into the following formula. Vdt = Vdmax - Vdmin [mV] 7. Line crawl Set to standard imaging condition II. Adjusting the luminous intensity so that the average value of the Gr signal output is 150mV, and then insert R, G and B filters and measure the difference between G signal lines (Glr, Glg, Glb [mV]) as well as the average value of the G signal output (Gar, Gag, Gab). Substitute the values into the following formula. Lci = Gli/Gai x 100 [%] (i = r, g, b) 8. Lag Adjust the Gr signal output value generated by strobe light to 150mV. After setting the strobe light so that it strobes with the following timing, measure the residual signal (Vlag). Substitute the value into the following formula. Lag = (Vlag/150) x 100 [%] VD Light Strobe light timing Gr signal output 150mV Output Vlag (lag) - 11 - Drive Circuit -7.5V 15V 3.3V 0.1F 1F/35V SHT 20 V3B 19 VL 18 0.1F V3A 17 V1B 16 VH 15 0.1F V1A 14 V4 13 V2 12 GND 11 2SC4250 1 V4 V3A V3B V2 V1A V1B 2 3 4 5 6 7 GND 8 VOUT 4.7k CCD OUT 100k 1 VDD 2 XSUB 3 XV3 4 XSG3B 5 XSG3A 7 XSG1B 8 XSG1A 9 XV4 10 XV1 CXD3400N 6 XV1 H2 H1 RG VL CSUB SUB GND VDD - 12 - VR1 (3.9k) ICX434DQN (BOTTOM VIEW) 16 15 14 13 12 11 10 9 0.1F 0.1F 1M 3.3F/16V 0.1F 3.3F/20V 0.01F VSUB Cont. H2 H1 RG ICX434DQN Drive Timing Chart (Vertical Sequence) High Frame Rate Readout Mode Frame Readout Mode/Electronic Shutter Exposure operation Act. Frame readout mode High frame rate readout mode High frame rate readout mode VD V1A V1B V2 V3A - 13 - B C CLOSE C output signal (ODD) C output signal (EVEN) V3B V4 D E A SUB TRG Mechanical shutter OPEN OPEN VSUB Cont. CCD OUT A output signal B output signal Output after frame readout D output signal E output signal ICX434DQN Note) The B output signal contains a blooming component and should therefore not be used. Drive Timing Chart (Vertical Sync) Frame Readout Mode Exposure period All pixel output period VD HD 10 23 26 30 35 675 660 645 650 673 680 685 1300 1 2 3 1 2 3 "c" "a" "c" "b" V1A/V1B V2 V3A/V3B 1 3 5 7 9 1 3 5 7 9 11 2 4 6 8 10 2 4 6 8 10 12 CCD OUT 1229 1231 1233 1235 1230 1232 1234 1236 - 14 - V4 SUB TRG Mechanical shutter OPEN CLOSE OPEN VSUB Cont. ICX434DQN Drive Timing Chart (Vertical Sync) Frame Readout Mode "a" Enlarged 1 56 188 1848 188 120 104 152 136 88 168 1027 1091 1071 H1 1 1848 56 72 120 V1A/V1B 152 104 V2 1071 136 V3A/V3B 1029 88 V4 - 15 - 200 1133 1131 184 1175 168 216 "b" Enlarged V1A/V1B V2 V3A/V3B V4 ICX434DQN Drive Timing Chart (Vertical Sync) Frame Readout Mode "c" Enlarged 42504 bits = 23 lines HD 56 1 56 V1A V1B - 16 - #3 #4 V2 V3A V3B V4 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 #1 #2 #758 ICX434DQN 1218 1223 1226 1231 1234 Drive Timing Chart (Vertical Sync) High Frame Rate Readout Mode 4 9 2 7 10 15 18 23 26 31 1218 1223 1226 1231 1234 4 9 2 7 10 15 18 23 26 31 - 17 - HD VD V3B V3A V1B V1A V4 V2 CCD OUT 320 325 1 2 3 4 5 10 "d" "d" 15 18 20 325 1 10 15 18 20 ICX434DQN Drive Timing Chart (Vertical Sync) High Frame Rate Readout Mode "d" Enlarged 56 H1 56 1848 1 188 1848 1 88 120 152 1091 88 120 152 V1A 1091 V1B 104 136 168 1133 72 104 136 168 V2 1131 1071 1175 V3A 1071 V3B 1029 1111 V4 188 1027 1071 - 18 - ICX434DQN Drive Timing Chart (Horizontal Sync) Frame Readout Mode 56 1848 1 188 CLK 1 1 1 132 1 56 1 RG SHP SHD 1 16 68 68 1 36 1 48 80 1 1 1 1 80 1 20 1 32 52 80 52 1 48 1 48 48 1 16 1 1 1 1 V1A V1B - 19 - 1 1 32 64 1 36 V2 V3A V3B V4 H1 H2 SUB 28 216 221 229 ICX434DQN Drive Timing Chart (Horizontal Sync) High Frame Rate Readout Mode 1848 1 188 216 221 1 1 229 CLK 1 1 126 1 56 RG SHP SHD 1 1 1 36 36 1 1 1 1 36 36 32 1 20 1 32 1 32 1 1 1 32 32 1 1 16 1 32 32 1 32 32 20 1 32 1 1 32 32 1 1 1 32 32 1 32 1 16 32 32 1 32 V1A V1B V2 - 20 - 1 1 32 64 1 36 V3A V3B V4 H1 H2 SUB 56 28 ICX434DQN ICX434DQN Notes on Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non-chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensors. e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges. 2) Soldering a) Make sure the package temperature does not exceed 80C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a 30W soldering iron with a ground wire and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering tool, use a thermal controller of the zero-cross On/Off type and connect it to ground. 3) Dust and dirt protection Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and dirt. Clean glass plates with the following operations as required, and use them. a) Perform all assembly operations in a clean room (class 1000 or less). b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. e) When a protective tape is applied before shipping, just before use remove the tape applied for electrostatic protection. Do not reuse the tape. 4) Installing (attaching) a) Remain within the following limits when applying a static load to the package. Do not apply any load more than 0.7mm inside the outer perimeter of the glass portion, and do not apply any load or impact to limited Cover glass 50N Plastic package Compressive strength 50N 1.2Nm Torsional strength b) If a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the bottom of the package. Therefore, for installation, use either an elastic load, such as a spring plate, or an adhesive. - 21 - ICX434DQN c) The adhesive may cause the marking on the rear surface to disappear, especially in case the regulated voltage value is indicated on the rear surface. Therefore, the adhesive should not be applied to this area, and indicated values should be transferred to other locations as a precaution. d) The notch of the package is used for directional index, and that can not be used for reference of fixing. In addition, the cover glass and seal resin may overlap with the notch of the package. e) If the leads are bent repeatedly and metal, etc., clash or rub against the package, the dust may be generated by the fragments of resin. f) Acrylate anaerobic adhesives are generally used to attach CCD image sensors. In addition, cyanoacrylate instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives. (reference) 5) Others a) Do not expose to strong light (sun rays) for long periods, as color filters will be discolored. When high luminous objects are imaged with the exposure level controlled by the electronic iris, the luminance of the image-plane may become excessive and discoloring of the color filter will possibly be accelerated. In such a case, it is advisable that taking-lens with the automatic-iris and closing of the shutter during the poweroff mode should be properly arranged. For continuous using under cruel condition exceeding the normal using condition, consult our company. b) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. c) Brown stains may be seen on the bottom or side of the package. But this does not affect the CCD characteristics. - 22 - Package Outline Unit: mm 16 pin SOP 5.0 9 9 16 (0.6) A 0.25 0.05 16 ~ 8.9 B 1.7 C 0 to 10 2.5 ~ 2.5 7.0 5.0 H 8 8 1 B' D 10.0 0.10 12.0 0.15 V 1.7 0.6 2.3 1 8.9 10.0 0.10 7.0 0.6 2.0 2.5 2.50 0.15 0.15 1.0 0.10 - 23 - ~ 1. "A" is the center of the effective image area. 2. The two points "B" of the package are the horizontal reference. The point "B'" of the package is the vertical reference. 0.64 3 0.47 0.30 0.15 0.3 5 6 7 8 9 M 4 The bottom "C" of the package, and the top of the cover glass "D" are the height reference. The center of the effective image area relative to "B" and "B" is (H, V) = (5.0, 5.0) 0.07mm. The rotation angle of the effective image area relative to H and V is 1. The height from the bottom "C" to the effective image area is 1.20 0.10mm. The height from the top of the cover glass "D" to the effective image area is 1.30 0.15mm. The tilt of the effective image area relative to the bottom "C" is less than 25m. The tilt of the effective image area relative to the top "D" of the cover glass is less than 25m. The thickness of the cover glass is 0.5mm, and the refractive index is 1.5. The notches on the bottom of the package are used only for directional index, they must not be used for reference of fixing. ICX434DQN 1.27 PACKAGE STRUCTURE PACKAGE MATERIAL Plastic LEAD TREATMENT GOLD PLATING LEAD MATERIAL 42 ALLOY PACKAGE MASS 0.50g Sony Corporation DRAWING NUMBER AS-D21(E) |
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